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Memory BW drops w/tight tertiary timings TridentX F3-2666C12-8GTXD on Asrock Z97 Pro4

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  • Radman3d
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    Prime64 custom memory test settings.
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  • Radman3d
    replied
    I have not messed with RTL/IOL, just letting them train on their own. I went ahead and set them to what you see in the pics and it did not seem make much of a difference. How low can I set RTL do you think? IOL is so low I'm leaving it alone for now. I normally test with Prime64 custom memory settings for 8-12 hours when I make changes.

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  • emissary42
    replied
    Could be your board failing to properly train the RTL/IOL with the reduced timings. You have to test that step by step. ATC shows the RTL/IOL on its main page, with MemTweakIt they are on a separate tab (#4 if I remember correctly).

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  • Radman3d
    replied
    RDWR, RDWRDR, RDWRDD all were at 15 now 16 and WRRDDD, WRWRDR, WRWRDD all were on 5 now 6. I have never been able to get the ASRock Timing Configurator to work right. MemTweakIt works though.


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  • emissary42
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    A screenshot of ASRock Timing Configurator and Aida Memory Benchmark would be helpful. Tightening which tertiary timing results in the drop of bandwidth?

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  • Memory BW drops w/tight tertiary timings TridentX F3-2666C12-8GTXD on Asrock Z97 Pro4

    I have been trying to improve the memory bandwidth of my TridentX F3-2666C12-8GTXD, two 8 GB sticks. So far I have got them to 11-13-12-30-1-270-7-16-8-8-28 (CL-RCD-RP-RAS-CR-RFC-RRD-WR-WTR-RTP-FAW) at 1.74 volts and SA at +.250. I have also tightened the tertiary timings. It seems like if I tighten the tertiary timings too much bandwidth suffers, but the latency still goes down. Latency going down is great, but bandwidth going down also is not good. Stability is good just do not understand why tight tertiary timings don’t equate to high bandwidth and low latency.
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