Hi Guys it's been a while ! I have been using my overclocked F3-12800CL8D-8GB 1600 Mhz RAM (overclocked to 2133MHz with no problems)
I would like some guidance with the secondary/third and Misc timings and how to improve these settings that my Asus Motherboard P8Z77-V has automatically set.
Here are all of my timings. Please note i don't need help with my primary timings these are 100% stable.
Primary Timings
DRAM Cas# Latency CHA: 11,CHB: 11
DRAM RAS# to CAS# Delay CHA: 11,CHB: 11
DRAM RAS# PRE Time CHA: 11,CHB: 11
DRAM RAS# ACT Time CHA: 11,CHB: 11
DRAM COMMAND Mode CHA: 1, CHB: 1
Secondary Timings
DRAM RAS# to RAS# Delay CHA: 7, CHB: 7
DRAM REF Cycle Time CHA: 171, CHB: 171
DRAM Refresh Interval CHA: 8320, CHB:8320
DRAM WRITE Recovery Time CHA: 16 CHB: 16
DRAM READ to PRE Time CHA:9 CHB: 9
DRAM FOUR ACT WIN Time CHA:33 CHB:33
DRAM WRITE to READ Delay CHA:9 CHB:9
DRAM CKE Minimum Pulse Width CHA:6 CHB:6
DRAM CAS# Write Latency CHA:8 CHB:8
DRAM RTL(CHA) CHA D0: 32,CHA D1:42
DRAM RTL (CHB) CHB D0: 32, CHB D1: 43
DRAM IO-L(CHA) CHA D0: 0, CHA D1: 3
DRAM IO-L(CHB) CHB D0: 0, CHB D1: 3
Third Timings
tWRDR (DD) CHA: 1,CHB: 1
tRWDR (DD) CHA: 4, CHB: 4
tRWSR CHA: 4, CHB:4
tRR(DD) CHA: 3, CHB: 3
tRR (DR) CHA:1 CHB:1
tRRSR CHA:4, CHB:4
tWW (DD) CHA:3, CHB:3
tWW (DR) CHA: 3, CHB:3
tWWSR CHA: 4, CHB:4
MISC
DRAM CLK Period Auto
Transmitter Slew(CHA) Auto
Transmitter Slew(CHB) Auto
Receiver Slew(CHA) Auto
Reciever Slew(CHB) Auto
MCH Duty Sense (CHA) Auto
MCH Duty Sense (CHB) Auto
Thanks for your help in advance
I would like some guidance with the secondary/third and Misc timings and how to improve these settings that my Asus Motherboard P8Z77-V has automatically set.
Here are all of my timings. Please note i don't need help with my primary timings these are 100% stable.
Primary Timings
DRAM Cas# Latency CHA: 11,CHB: 11
DRAM RAS# to CAS# Delay CHA: 11,CHB: 11
DRAM RAS# PRE Time CHA: 11,CHB: 11
DRAM RAS# ACT Time CHA: 11,CHB: 11
DRAM COMMAND Mode CHA: 1, CHB: 1
Secondary Timings
DRAM RAS# to RAS# Delay CHA: 7, CHB: 7
DRAM REF Cycle Time CHA: 171, CHB: 171
DRAM Refresh Interval CHA: 8320, CHB:8320
DRAM WRITE Recovery Time CHA: 16 CHB: 16
DRAM READ to PRE Time CHA:9 CHB: 9
DRAM FOUR ACT WIN Time CHA:33 CHB:33
DRAM WRITE to READ Delay CHA:9 CHB:9
DRAM CKE Minimum Pulse Width CHA:6 CHB:6
DRAM CAS# Write Latency CHA:8 CHB:8
DRAM RTL(CHA) CHA D0: 32,CHA D1:42
DRAM RTL (CHB) CHB D0: 32, CHB D1: 43
DRAM IO-L(CHA) CHA D0: 0, CHA D1: 3
DRAM IO-L(CHB) CHB D0: 0, CHB D1: 3
Third Timings
tWRDR (DD) CHA: 1,CHB: 1
tRWDR (DD) CHA: 4, CHB: 4
tRWSR CHA: 4, CHB:4
tRR(DD) CHA: 3, CHB: 3
tRR (DR) CHA:1 CHB:1
tRRSR CHA:4, CHB:4
tWW (DD) CHA:3, CHB:3
tWW (DR) CHA: 3, CHB:3
tWWSR CHA: 4, CHB:4
MISC
DRAM CLK Period Auto
Transmitter Slew(CHA) Auto
Transmitter Slew(CHB) Auto
Receiver Slew(CHA) Auto
Reciever Slew(CHB) Auto
MCH Duty Sense (CHA) Auto
MCH Duty Sense (CHB) Auto
Thanks for your help in advance

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