Tweet
How far G.SKILL Ripjaws X Series (F3-14900CL8D-8GBXM) go...?
I wonder, how fast these DDR3 rams can go - G.SKILL Ripjaws X Series F3-14900CL8D-8GBXM:
And what chips they use - so if there is a chance for getting them run faster with more voltage - and what is the safe (or reasonably safe?) voltage limit for them.
That, of course, apply only when the chips used react well to more voltage. So, since the G.Skill logo claims "Go Beyond Limits", then I put these poor rams into Asus Z97-Pro (WiFi ac) board. Upon activating the XMP profile by switch on the board, the rams run at 8-9-9-24 2T @ 1866MHz.
The 2T can be changed to 1T and at that point, it gives with not overclocked i7 4790K, 21 739MB/sec in Memtest 4.20. The voltage is default 1.50V. When tried to set the DDR3-2000MHz memory clock settings, the board failed to post. 1866 seems to be the maximum at such settings (rest is on auto ATM). Precise settings are bellow (most "auto" values report what they are in the bios, what is marked with "???" is not shown up - does not show it's current settig in the bios).
The question is - of course - what best settings to use for these rams (there seems to be plenty of settings, including skews) and what one can expect to get from them on tight timings. Or if relaxing the timings help to get higher and that produce faster result...?
I checked the DDR3 ram chips list there:
http://ramlist.i4memory.com/ddr3/
...yet the closest I found was: PC3-14900 Ripjaws X
F3-14900CL9D-8GBXL (2x4GB) - 9-10-9-28 @ 1.5V - Hynix H5TQ2G83CFR-H9C
Close, but no hit. So that is not exactly helpfull. And since the rams run cold (several memtest hours) at 1.50V, then I believe they might like more voltage
So the question is only how much, or what settings will be optimal to use to get them higher. IIRC the framerate in games stop increasing at about 2100MHz, so reaching the 2000 would be cool.
Is this possible?
The Asus Z97-Pro (WiFi ac) mainboard offer these settings for memory:
Primary Timings
DRAM CAS# Latency [Auto] [1] – [31] - 8
DRAM RAS# to CAS# Delay [1] – [31] - 9
DRAM RAS# PRE Time [Auto] [1] – [31] - 9
DRAM RAS# ACT Time [Auto] [1] – [63] - 24
DRAM Command Rate [Auto] [1] – [2] - 1
Secondary Timings
DRAM RAS# to RAS# Delay [Auto] [1] – [15] - 6
DRAM REF Cycle Time [Auto] [1] – [511] - 243
DRAM Refresh Interval [Auto] [1] – [65535] - 7283
DRAM WRITE Recovery Time [Auto] [1] – [16] - ???
DRAM READ to PRE Time [Auto] [1] – [15] - 8
DRAM FOUR ACT WIN Time [Auto] [1] – [255] - 29
DRAM WRITE to READ Delay [Auto] [1] – [15] - ???
DRAM CKE Minimum Pulse Width [Auto] [1] – [15] - 5
DRAM CAS# Write Latency [Auto] [1] – [31] - 8
RTL IOL control
DRAM RTL Initial Value [Auto] [1] - [63] - Auto
DRAM RTL (CHA_R0D0) [Auto] [1] - [63] - 0
DRAM RTL (CHA_R0D1) [Auto] [1] - [63] - 37
DRAM RTL (CHA_R1D0) [Auto] [1] - [63] - 0
DRAM RTL (CHA_R1D1) [Auto] [1] - [63] - 0
DRAM RTL (CHB_R0D0) [Auto] [1] - [63] - 0
DRAM RTL (CHB_R0D1) [Auto] [1] - [63] - 37
DRAM RTL (CHB_R1D0) [Auto] [1] - [63] - 0
DRAM RTL (CHB_R1D1) [Auto] [1] - [63] - 0
DRAM IO-L (CHA_R0D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHA_R0D1) [Auto] [1] - [15] - 4
DRAM IO-L (CHA_R1D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHA_R1D1) [Auto] [1] - [15] - 0
DRAM IO-L (CHB_R0D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHB_R0D1) [Auto] [1] - [15] - 4
DRAM IO-L (CHB_R1D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHB_R1D1) [Auto] [1] - [15] - 0
Third Timings
tRDRD [Auto] [1] - [7] - 4
tRDRD_dr [Auto] [1] - [15] - 6
tRDRD_dd [Auto] [1] - [15] - 6
tWRRD [Auto] [1] - [63] - 22
tWRRD_dr [Auto] [1] - [15] - 7
tWRRD_dd [Auto] [1] - [15] - 7
tWRWR [Auto] [1] - [7] - 4
tWRWR_dr [Auto] [1] - [15] - 7
tWRWR_dd [Auto] [1] - [15] - 7
Dec_WRD [Auto] [0] [1] - ???
tRDWR [Auto] [1] - [31] - 9
tRDWR_dr [Auto] [1] - [31] - 9
tRDWR_dd [Auto] [1] - [31] - 9
Skew Control
Transmitter Rising Slope [Auto] [0] – [31] - Auto
Transmitter Falling Slope [Auto] [0] – [31] - Auto
Transmitter Control Time [Auto] [0] – [31] - Auto
Receiver Rising Slope [Auto] [0] – [31] - Auto
Receiver Falling Slope [Auto] [0] – [31] - Auto
Receiver Control Time [Auto] [0] – [31] - Auto
MRC Fast Boot [Auto] [Enabled] [Disabled] - Enabled
DRAM CLK Period [Auto] [1] – [14] - Auto
Channel A/B DIMM Control [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1] [Disable Both DIMMS] - Enable Both DIMMS
Scrambler Setting [Optimized (ASUS] [Default (MRC)] - Optimized (ASUS)
MCH Full Check [Auto] [Enabled] [Disabled] - Auto
And what chips they use - so if there is a chance for getting them run faster with more voltage - and what is the safe (or reasonably safe?) voltage limit for them.
That, of course, apply only when the chips used react well to more voltage. So, since the G.Skill logo claims "Go Beyond Limits", then I put these poor rams into Asus Z97-Pro (WiFi ac) board. Upon activating the XMP profile by switch on the board, the rams run at 8-9-9-24 2T @ 1866MHz.
The 2T can be changed to 1T and at that point, it gives with not overclocked i7 4790K, 21 739MB/sec in Memtest 4.20. The voltage is default 1.50V. When tried to set the DDR3-2000MHz memory clock settings, the board failed to post. 1866 seems to be the maximum at such settings (rest is on auto ATM). Precise settings are bellow (most "auto" values report what they are in the bios, what is marked with "???" is not shown up - does not show it's current settig in the bios).
The question is - of course - what best settings to use for these rams (there seems to be plenty of settings, including skews) and what one can expect to get from them on tight timings. Or if relaxing the timings help to get higher and that produce faster result...?
I checked the DDR3 ram chips list there:
http://ramlist.i4memory.com/ddr3/
...yet the closest I found was: PC3-14900 Ripjaws X
F3-14900CL9D-8GBXL (2x4GB) - 9-10-9-28 @ 1.5V - Hynix H5TQ2G83CFR-H9C
Close, but no hit. So that is not exactly helpfull. And since the rams run cold (several memtest hours) at 1.50V, then I believe they might like more voltage
So the question is only how much, or what settings will be optimal to use to get them higher. IIRC the framerate in games stop increasing at about 2100MHz, so reaching the 2000 would be cool.Is this possible?
The Asus Z97-Pro (WiFi ac) mainboard offer these settings for memory:
Primary Timings
DRAM CAS# Latency [Auto] [1] – [31] - 8
DRAM RAS# to CAS# Delay [1] – [31] - 9
DRAM RAS# PRE Time [Auto] [1] – [31] - 9
DRAM RAS# ACT Time [Auto] [1] – [63] - 24
DRAM Command Rate [Auto] [1] – [2] - 1
Secondary Timings
DRAM RAS# to RAS# Delay [Auto] [1] – [15] - 6
DRAM REF Cycle Time [Auto] [1] – [511] - 243
DRAM Refresh Interval [Auto] [1] – [65535] - 7283
DRAM WRITE Recovery Time [Auto] [1] – [16] - ???
DRAM READ to PRE Time [Auto] [1] – [15] - 8
DRAM FOUR ACT WIN Time [Auto] [1] – [255] - 29
DRAM WRITE to READ Delay [Auto] [1] – [15] - ???
DRAM CKE Minimum Pulse Width [Auto] [1] – [15] - 5
DRAM CAS# Write Latency [Auto] [1] – [31] - 8
RTL IOL control
DRAM RTL Initial Value [Auto] [1] - [63] - Auto
DRAM RTL (CHA_R0D0) [Auto] [1] - [63] - 0
DRAM RTL (CHA_R0D1) [Auto] [1] - [63] - 37
DRAM RTL (CHA_R1D0) [Auto] [1] - [63] - 0
DRAM RTL (CHA_R1D1) [Auto] [1] - [63] - 0
DRAM RTL (CHB_R0D0) [Auto] [1] - [63] - 0
DRAM RTL (CHB_R0D1) [Auto] [1] - [63] - 37
DRAM RTL (CHB_R1D0) [Auto] [1] - [63] - 0
DRAM RTL (CHB_R1D1) [Auto] [1] - [63] - 0
DRAM IO-L (CHA_R0D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHA_R0D1) [Auto] [1] - [15] - 4
DRAM IO-L (CHA_R1D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHA_R1D1) [Auto] [1] - [15] - 0
DRAM IO-L (CHB_R0D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHB_R0D1) [Auto] [1] - [15] - 4
DRAM IO-L (CHB_R1D0) [Auto] [1] - [15] - 0
DRAM IO-L (CHB_R1D1) [Auto] [1] - [15] - 0
Third Timings
tRDRD [Auto] [1] - [7] - 4
tRDRD_dr [Auto] [1] - [15] - 6
tRDRD_dd [Auto] [1] - [15] - 6
tWRRD [Auto] [1] - [63] - 22
tWRRD_dr [Auto] [1] - [15] - 7
tWRRD_dd [Auto] [1] - [15] - 7
tWRWR [Auto] [1] - [7] - 4
tWRWR_dr [Auto] [1] - [15] - 7
tWRWR_dd [Auto] [1] - [15] - 7
Dec_WRD [Auto] [0] [1] - ???
tRDWR [Auto] [1] - [31] - 9
tRDWR_dr [Auto] [1] - [31] - 9
tRDWR_dd [Auto] [1] - [31] - 9
Skew Control
Transmitter Rising Slope [Auto] [0] – [31] - Auto
Transmitter Falling Slope [Auto] [0] – [31] - Auto
Transmitter Control Time [Auto] [0] – [31] - Auto
Receiver Rising Slope [Auto] [0] – [31] - Auto
Receiver Falling Slope [Auto] [0] – [31] - Auto
Receiver Control Time [Auto] [0] – [31] - Auto
MRC Fast Boot [Auto] [Enabled] [Disabled] - Enabled
DRAM CLK Period [Auto] [1] – [14] - Auto
Channel A/B DIMM Control [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1] [Disable Both DIMMS] - Enable Both DIMMS
Scrambler Setting [Optimized (ASUS] [Default (MRC)] - Optimized (ASUS)
MCH Full Check [Auto] [Enabled] [Disabled] - Auto
Comment