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Prime95 Errors at Stock - Seems to be Sub-timings?

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  • Prime95 Errors at Stock - Seems to be Sub-timings?

    Hi!

    I have 2 separate matched pairs of GSkill, so 4 sticks in total. I know there can be compatibility issues when using separate pairs, but in this instance it has served to help my diagnosis of the titled issue. First of all the specs:

    i5 3570K (Ivy Bridge) @ 3.5Ghz when stock
    Asus Maximus V Formula
    GSkill DDR3-1600 9-9-9-24-2N (F3-12800CL9D-8GBXL) (16GB total - 2 matched pairs of 2x4GB)

    I don't know if it's useful or not, but based on some quick Googling I get the following IC info based on the both pairs' S/Ns:

    Pair 1 - 12xx1800xxxxxx (2012. "Eplida" ICs)
    Pair 2 - 13xx1200xxxxxx (2013. "Powerchip/PSC (sometimes eTT/uTT)" ICs)

    As for the titled issue, it's only a problem with Pair 2. Pair 1 sees none of the listed issues, so I removed them from my system to focus on Pair 2 in isolation.

    When going for a higher overclock I noticed I was getting a lot of errors in Prime95 (v26.6, v27.9, & v28.5) in the larger FFT sizes, specifically in range of 160K-1920K. Most of the time they occur in the mid-hundreds though, with the first 15 min test of Blend (384K FFT size using P95 v28.5) being all that's needed half the time. These larger FFT sizes led me to thinking the issue was something Ram<->IMC related, rather than the cache or cores.

    I'm going to cut out a lot of my problem solving steps now and just say the error occurs regardless of CPU freq, whether oc'ed to 4.4Ghz, at stock, or downclocked to 3.0Ghz; when the ram frequency is dropped to 1333 and the ram voltage raised from 1.50v to 1.55v; raising VCCSA and/or VCCIO; going through VRM control settings; whether using memory channel A or B; different power supplies.

    I'll clarify or fill in any extra detail on those steps if necessary.

    As for why I believe it's timings-related:

    On my ASUS mb I can use 'XMP' or 'Auto', as well as something called 'Maximus Tweak' providing a 'Mode 1' and 'Mode 2' that appear to adjust the subtimings. 'Mode 1' looks more relaxed than 'Mode 2'. I went through the various settings (ie. Auto vs XMP, 1600 vs 1333, Mode 1 vs Mode 2) and the combinations thereof, doing P95 tests as I went, all of which failed. However, in looking at those different combinations I did notice that some timings didn't vary much. At this point I opted to go through and loosen everything manually (whilst keeping what timings relationships I knew about in mind, as in tX+tY<=tZ). I was getting full passes with Prime95. Curious, I starting using a bit of divide-and-conquer where half the timings were kept tight and the other half loose, narrowing it down. I eventually arrived at the 'Write Recovery Time (tWR)' timing. Assuming I've been doing nothing wrong up to this point, all other values appear to be fine at their XMP defaults, but this setting - 'tWR' - won't give me a pass unless at '16'. At all the various defaults i've seen (eg. 1333, Mode 2, XMP, etc) it's always either '10' or '12'. Some quick tests at a slightly smaller increase to '14' also fails. Raising the DRAM voltage just doesn't seem to change the stability of it.

    Are the subtimings used based on fixed data found on the ram, or is it auto-determined? Is this considered faulty ram? Is an issue with that specific timing an indication of anything? Thoughts?

    I would have stopped sooner and gone for a 2x8GB kit, but aside from the low DDR3 stock and high prices I'm seeing where I am, I needed to be certain of where the problem lied first anyway.

    Thanks for any info or help you can provide.
    Last edited by Anonagrog; 11-28-2016, 07:09 AM.

  • #2
    tWR should be 12 for DDR3-1600, 10 for DDR3-1333

    There are memory profiles and timings the BIOS can choose from when set to AUTO.

    To determine whether a stick is bad, load BIOS defaults, enable XMP and see if each stick can pass. It should use the same settings for each, so there should be no timing issue.

    If you can post a picture of memory timings, we can confirm they are correct.

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