RAMMon v1.0 Build: 1015 built with SysInfo v1.0 Build: 1097 PassMark (R) Software www.passmark.com Memmory summary for BOXER-PC: Number of Memory Devices: 2 Total Physical Memory: 4094 MB (4096 MB) Total Available Physical Memory: 2578 MB Memory Load: 37% Item | Slot #1 | Slot #2 | Slot #3 | Slot #4 | -------------------------------------------------------------------------------|--------------------|--------------------|-----------------|-----------------|- Ram Type | DDR2 | DDR2 | Not Populated | Not Populated | Maximum Clock Speed (MHz) | 400 (JEDEC) | 400 (JEDEC) | | | Maximum Transfer Speed (MHz) | DDR2-800 | DDR2-800 | | | Maximum Bandwidth (MB/s) | PC2-6400 | PC2-6400 | | | Memory Capacity (MB) | 2048 | 2048 | | | Jedec Manufacture Name | G Skill Intl | G Skill Intl | | | Search Amazon.com | Search! | Search! | | | SPD Revision | 1.2 | 1.2 | | | Registered | No | No | | | ECC | No | No | | | DIMM Slot # | 1 | 2 | | | Manufactured | | | | | Module Part # | F2-8500CL5-2GBPK | F2-8500CL5-2GBPK | | | Module Revision | 0x0 | 0x0 | | | Module Serial # | 0x0 | 0x0 | | | Module Manufacturing Location | 0 | 0 | | | # of Row Addressing Bits | 14 | 14 | | | # of Column Addressing Bits | 10 | 10 | | | # of Banks | 8 | 8 | | | # of Ranks | 2 | 2 | | | Device Width in Bits | 8 | 8 | | | Bus Width in Bits | 64 | 64 | | | Module Voltage | SSTL 1.8V | SSTL 1.8V | | | CAS Latencies Supported | 4 5 | 4 5 | | | Timings @ Max Frequency (JEDEC) | 5-5-5-15 | 5-5-5-15 | | | Maximum frequency (MHz) | 400 | 400 | | | Maximum Transfer Speed (MHz) | DDR2-800 | DDR2-800 | | | Maximum Bandwidth (MB/s) | PC2-6400 | PC2-6400 | | | Minimum Clock Cycle Time, tCK (ns) | 2.500 | 2.500 | | | Minimum CAS Latency Time, tAA (ns) | 12.500 | 12.500 | | | Minimum RAS to CAS Delay, tRCD (ns) | 12.500 | 12.500 | | | Minimum Row Precharge Time, tRP (ns) | 12.500 | 12.500 | | | Minimum Active to Precharge Time, tRAS (ns) | 37.000 | 37.000 | | | Minimum Row Active to Row Active Delay, tRRD (ns) | 7.500 | 7.500 | | | Minimum Auto-Refresh to Active/Auto-Refresh Time, tRC (ns) | 60.000 | 60.000 | | | Minimum Auto-Refresh to Active/Auto-Refresh Command Period, tRFC (ns) | 127.500 | 127.500 | | | | | | | | DDR2 Specific SPD Attributes | | | | | Data Access Time from Clock, tAC (ns) | 0.400 | 0.400 | | | Clock Cycle Time at Medium CAS Latency (ns) | 3.750 | 3.750 | | | Data Access Time at Medium CAS Latency (ns) | 0.500 | 0.500 | | | Clock Cycle Time at Short CAS Latency (ns) | 5.000 | 5.000 | | | Data Access Time at Short CAS Latency (ns) | 0.600 | 0.600 | | | Maximum Clock Cycle Time (ns) | 8.000 | 8.000 | | | Write Recover Time, tWR (ns) | 15.000 | 15.000 | | | Internal Write to Read Command Delay, tWTR (ns) | 7.500 | 7.500 | | | Internal Read to Precharge Command Delay, tRTP (ns) | 7.500 | 7.500 | | | Address/Command Setup Time Before Clock, tIS (ns) | 0.170 | 0.170 | | | Address/Command Hold Time After Clock, tIH (ns) | 0.250 | 0.250 | | | Data Input Setup Time Before Strobe, tDS (ns) | 0.050 | 0.050 | | | Data Input Hold Time After Strobe, tDH (ns) | 0.120 | 0.120 | | | Maximum Skew Between DQS and DQ Signals (ns) | 0.200 | 0.200 | | | Maximum Read Data hold Skew Factor (ns) | 0.240 | 0.240 | | | PLL Relock Time (ns) | 0.000 | 0.000 | | | DRAM Package Type | Planar | Planar | | | Burst Lengths Supported | 4 8 | 4 8 | | | Refresh Rate | Reduced (7.8us) | Reduced (7.8us) | | | # of PLLS on DIMM | 0 | 0 | | | FET Switch External Enable | No | No | | | Analysis Probe Installed | No | No | | | Weak Driver Supported | Yes | Yes | | | 50 Ohm ODT Supported | Yes | Yes | | | Partial Array Self Refresh Supported | Yes | Yes | | | Module Type | UDIMM | UDIMM | | | Module Height (mm) | 30.0 | 30.0 | | |