Hallo!
According to the "Datasheet Volume 2" for Intel processors in the LGA2011-v3 package (5th gen Core i7 5xxx series and Xeon) the maximum number of DIMM sockets per DRAM channel is limited to 3. G.SKILL sets the "Channel Config" parameter of XMP 2.0 to 4 for all DDR4 memory modules with XMP 2.0. This seems to be strange. So, is it supposed to be a mistake of G.SKILL FAE? Thanks!
According to the "Datasheet Volume 2" for Intel processors in the LGA2011-v3 package (5th gen Core i7 5xxx series and Xeon) the maximum number of DIMM sockets per DRAM channel is limited to 3. G.SKILL sets the "Channel Config" parameter of XMP 2.0 to 4 for all DDR4 memory modules with XMP 2.0. This seems to be strange. So, is it supposed to be a mistake of G.SKILL FAE? Thanks!
Comment